1. Field of the Invention
The present invention relates to a method and device for producing a layout pattern of a semiconductor device.
2. Description of the Related Art
Recent fabrication methods of semiconductor devices are described below. First, wells are formed close to the wafer surface and impurities are injected into the wells to form diffusion layers. Thereafter trenches are formed in element isolation areas for isolating each element. An oxide film (insulating film) is then formed by a well-known CVD (Chemical Vapor Deposition) method over the entire surface of the wafer including the interiors of the trenches. The surface of the formed oxide film is uneven, that is, is higher at the diffusion layers and lower at the trenches. A known CMP (Chemical Mechanical Polishing) method is then carried out to planarize the wafer surface, so that the oxide film of the wafer surface is removed to expose the surface of the diffusion layers. At this time, polishing proceeds further in regions of the wafer surface having few diffusion layers than in areas having many diffusion layers, raising the problem of excessive abrasion of the wafer surface. In other words, there is the problem that the amount of abrasion of the wafer surface differs depending on the distribution of the diffusion layers.
These problems in processing the wafer surface accompany miniaturization of semiconductor devices. In semiconductor devices of the prior art in which sufficient separation was provided between diffusion layers and between trenches to prevent unevenness in the oxide film surface from adversely affecting subsequent processes, planarization was not required and the above-described problem did not occur.
One known and typical method for creating a layout pattern of a semiconductor device involves arranging fill cells (also referred to as “dummy cells”), composed only of wells, in vacant areas that lack circuit patterns. In this method, a semiconductor device is fabricated by making mask data from a layout pattern that includes fill cells, fabricating a reticle based on this mask data, and then forming diffusion layers or wiring layers by using the reticle. Nevertheless, such an arrangement of fill cells composed only of wells in vacant areas cannot solve the above-described problems in processing the wafer surface.
In order to solve the aforementioned problems in processing the wafer surface, it is contemplated that, after creating the layout pattern of a semiconductor device, dummy data of diffusion layers are inserted in a mask data of areas having few diffusion layers when making mask data, whereby the distribution of diffusion layers is made uniform. However, a method in which dummy data are added to the mask data when making mask data is problematic because the distribution of diffusion layers and the size of vacant areas must be calculated from the layout pattern, and this calculation entails complex arithmetic processes and an excessive amount of processing time.
In addition, a method is also known in which the fill cells arranged in vacant areas have the same construction as transistors with gate electrodes. For example, Japanese Patent Laid-Open Publication No. 176941/99 (hereinbelow referred to as “Patent Document 1”) discloses a construction in which dummy cells with wiring are arranged in vacant areas that is generated after each of the constituent elements of the semiconductor device have been arranged. In Patent Document 1, dummy cells with wiring such that the wiring data ratio (the wiring data ratio being the proportion of the wiring area) falls within a prescribed range, are arranged in vacant areas. This arrangement is directed toward solving the problem that a low wiring data ratio prevents the accurate formation of a wiring pattern when forming wiring. In other words, Patent Document 1 addresses problems relating to the distribution of wiring formed on the upper layer of a wafer after transistors have been formed on the wafer. The dummy cells used in Patent Document 1 include p-channel MOS transistors and n-channel MOS transistors and therefore contain diffusion layers. However, since the problem addressed by Patent Document 1 is the distribution of wiring such as gate electrodes as described above, there is no disclosure regarding the significance of the distribution of diffusion layers in Patent Document 1.